This invention relates to programmable logic array integrated circuit devices, and more particularly to improved features for such devices (e.g., improved embedded array block (EAB) circuitry that allows EABs to be more easily combined to get deeper random access memory (RAM)).
Programmable logic array integrated circuit devices are well known, as shown, for example by Pedersen et al. U.S. Pat. No. 5,260,610, Cliff et al. U.S. Pat. No. 5,260,611, Cliff et al. U.S. Pat. No. 5,550,782, and Cliff et al. U.S. Pat. No. 5,689,195 (which are hereby incorporated by reference herein). Such devices often include a large number of regions of programmable logic disposed on the device in a two-dimensional array of intersecting "rows" and "columns" of such regions. Each region is programmable to perform any of several logic functions on signals applied to the region. Each row may have associated "horizontal" conductors for conveying signals to, from, and/or between the regions in the row. Each column may have associated "vertical" conductors for conveying signals to, from, and/or between the rows. Programmable connections may be provided for selectively connecting the conductors adjacent to each region to the inputs and outputs of the region, and also for selectively connecting various conductors to one another (e.g., connecting a horizontal conductor to a vertical conductor). Interconnection of regions through the above-mentioned conductors and programmable connections makes it possible for the programmable logic array device to perform much more complicated logic functions than can be performed by the individual regions.
In addition to the above-described interconnection of regions of programmable logic, programmable logic array integrated circuit devices sometimes include a number of regions of random access memory or RAM (herein referred to as embedded array blocks (EABs)) that are programmable and usable by the user to store and output any desired data. The '195 patent, for example, discusses the use and operation of RAM in a programmable logic array device.
Typically, EABs are fixed in size (e.g., 2K programmable bits) and can be configured as a 258.times.8, 512.times.4, 1042.times.2, or 2048.times.1 EAB. To get wider EABs with a depth up to 2K, multiple EABs may be combined in parallel (e.g., using eight 2048.times.1 EABs to make a 2048.times.8 EAB). In the prior art, however, to make EABs deeper than 2K required considerable external logic to perform address decoding and data multiplexing. This external logic may affect the timing of the EAB.
In view of the foregoing, it is an object of this invention to provide improved EABs for use in programmable logic array devices.
It is a more particular object of this invention to provide improved EABs which can be easily and efficiently combined to provide EABS with depths greater than 2K.